Interactive multi-level failsafe enablement

ABSTRACT

Embodiments include method, systems and computer program products for an interactive, multi-level failsafe capability. In some embodiments, a failed count indicative of a number of failed attempts to launch an application may be received. A failsafe mode level corresponding to the failed count may be determined. The failsafe mode level may be initialized in response to determining the failsafe mode level corresponding to the failed count. The failsafe mode level may determine the functionality that may be enabled. Users may perform interactive debugging by editing configuration settings and manually enabling functionality.

The following disclosure(s) are submitted under 35 U.S.C. §102(b)(1)(A): DISCLOSURE: IBM DataPower Gateway Firmware V7.2 provides increased cloud deployment flexibility and mobile security enhancements, May 26, 2015.

BACKGROUND

The present disclosure relates to methods, systems and computer program products for an interactive multi-level failsafe capability.

Devices are often designed to include a failsafe mode. In critical error scenarios, the device enters this mode to prevent or minimize the harm to the device or other entity. When in failsafe mode, users have limited capabilities but are often enabled to save important data and view error messages. Users are sometimes able to correct certain type of problems if the error messages are sufficiently informative.

Failsafe mode designs can be seen in many types of products. For example, failsafe mode for traffic lights would result in the lights flashing when an error condition occurs. In the software world, a failsafe mode in an operating system may be initialized when faulty drivers are installed or when some program prevents the system from loading normally. In these types of environments, the system may enter failsafe mode, where many capabilities are disabled and users are not allowed to enable them in the failsafe mode.

SUMMARY

In accordance with an embodiment, a computer-implemented method for establishing a failsafe mode for an electronic device may be provided. The method may include receiving a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determining a failsafe mode level corresponding to the failed count; and initializing the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.

In another embodiment, a computer program product for establishing a failsafe mode for an electronic device may include a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising receiving a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determining a failsafe mode level corresponding to the failed count; and initializing the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.

In another embodiment, a system for establishing a failsafe mode for an electronic device may include a processing unit in communication with one or more types of memory, where the processing unit may be configured to receive a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determine a failsafe mode level corresponding to the failed count; and initialize the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features, and advantages of the disclosure are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating one example of a processing system for practice of the teachings herein;

FIG. 2 is a block diagram illustrating a computing system in accordance with an exemplary embodiment; and

FIG. 3 is a flow diagram of a method for an interactive multi-level failsafe enabling program in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

In accordance with exemplary embodiments of the disclosure, methods, systems and computer program products with an interactive multi-level failsafe capability. This disclosure is directed to a failsafe enabling program that may be used during exercises, such as, to diagnose and correct problems through live software debugging.

In some embodiments, the interactive multi-level failsafe enabling program may have multiple failsafe levels. Each level may differ from the next in terms of enabled functionality. A failed count is maintained of the number of start-up attempts and may be used to determine the failsafe mode level that the system enters. As the number of attempts increases, the failsafe mode level increases and becomes more and more restrictive in terms of automatically enabled functionality; in other words, there may be a direct relationship between the increase in the failsafe mode level and the program automatically disabling software and/or hardware functionality. In some embodiments, users may manually enable functionality that was disabled as the system entered their specific level of failsafe mode. This capability allows users to perform live-debugging of their environment. For example, if some feature was disabled, they can examine the configuration settings for that feature and if it looks suspicious, they may enable only that feature and observe the results. If enabling the feature resulted in system failure, then the user would have identified a problem that needs to be corrected. The user could then proceed to modify the configuration and enable the feature once again.

The different failsafe mode levels may each have varying degrees of functionality. Additionally, each configuration or command of a computing system may be assigned a failsafe mode level indicating at what levels of failsafe mode initialization it can be enabled. Additionally, after failsafe model level initialization, all commands may be enabled manually.

Referring to FIG. 1, there is shown an embodiment of a processing system 100 for implementing the teachings herein. In this embodiment, the system 100 has one or more central processing units (processors) 101 a, 101 b, 101 c, etc. (collectively or generically referred to as processor(s) 101). In one embodiment, each processor 101 may include a reduced instruction set computer (RISC) microprocessor. Processors 101 are coupled to system memory 114 and various other components via a system bus 113. Read only memory (ROM) 102 is coupled to the system bus 113 and may include a basic input/output system (BIOS), which controls certain basic functions of system 100.

FIG. 1 further depicts an input/output (I/O) adapter 107 and a network adapter 106 coupled to the system bus 113. I/O adapter 107 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 103 and/or tape storage drive 105 or any other similar component. I/O adapter 107, hard disk 103, and tape storage device 105 are collectively referred to herein as mass storage 104. Operating system 120 for execution on the processing system 100 may be stored in mass storage 104. A network adapter 106 interconnects bus 113 with an outside network 116 enabling data processing system 100 to communicate with other such systems. A screen (e.g., a display monitor) 115 is connected to system bus 113 by display adapter 112, which may include a graphics adapter to improve the performance of graphics intensive applications and a video controller. In one embodiment, adapters 107, 106, and 112 may be connected to one or more I/O busses that are connected to system bus 113 via an intermediate bus bridge (not shown). Suitable I/O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols, such as the Peripheral Component Interconnect (PCI). Additional input/output devices are shown as connected to system bus 113 via user interface adapter 108 and display adapter 112. A keyboard 109, mouse 110, and speaker 111 all interconnected to bus 113 via user interface adapter 108, which may include, for example, a Super I/O chip integrating multiple device adapters into a single integrated circuit.

In exemplary embodiments, the processing system 100 includes a graphics-processing unit 130. Graphics processing unit 130 is a specialized electronic circuit designed to manipulate and alter memory to accelerate the creation of images in a frame buffer intended for output to a display. In general, graphics-processing unit 130 is very efficient at manipulating computer graphics and image processing, and has a highly parallel structure that makes it more effective than general-purpose CPUs for algorithms where processing of large blocks of data is done in parallel.

Thus, as configured in FIG. 1, the system 100 includes processing capability in the form of processors 101, storage capability including system memory 114 and mass storage 104, input means such as keyboard 109 and mouse 110, and output capability including speaker 111 and display 115. In one embodiment, a portion of system memory 114 and mass storage 104 collectively store an operating system such as the AIX® operating system from IBM Corporation to coordinate the functions of the various components shown in FIG. 1.

Referring now to FIG. 2, a computing system 200 in accordance with an embodiment is illustrated. As illustrated, the computing system 200 may include, but is not limited to a supervisor module 210 and a main program 215. The main program 215 may include a command line interface 230.

The supervisor module 210 may include computer-readable instructions that, in response to execution by the processor(s) 101, cause operations to be performed including monitoring the execution and processing of one or more applications (e.g., main program 215) and tools. The supervisor module 210 may also maintain a failed count that is indicative of the number of failed attempts to launch the main program 215 and may be responsible for launching or initiating the main program 215.

The main program 215 may include computer-readable instructions that, in response to execution by the processor(s) 101, cause operations to be performed including monitoring networks connections, data processing, or the like.

The main program 215 may include computer-readable instructions that, in response to execution by the processor(s) 101, cause operations to be performed including determining a failsafe mode level to initialize based on the failed count received from the supervisor module 210. The main program 215 may enable one or more configuration, command, and/or functionality based on input received from a user. In some embodiments, the main program 215 may communicate with the supervisor module 210 to increment or reset the failed count.

The command line interface 230 may include computer-readable instructions that, in response to execution by the processor(s) 101, cause operations to be performed including generating an interface to present to the user and to receive input via the interface. In some embodiments, the command line interface may be used to issue a command to the main program 215 to reset the failed count. In some embodiment, the command line interface 230 may be used to issue a command to the main program 215 to set the failed count to a specific number. In some embodiments, the command line interface 230 may be included in the main program 215 to enable the user to activate functionality and edit settings of the main program 215 while in a failsafe mode; in other words, to enable the user to effectively override the failsafe mode.

Referring now to FIG. 3, a flow diagram of a method 300 for an interactive multi-level capability in accordance with an exemplary embodiment is shown.

At block 305, the main program 215 may receive a failed count indicative of a number of failed attempts to launch an application (e.g., main program 215). In some embodiments, the supervisor module 210 may maintain the failed count and may transmit the failed count to the main program 215. In some embodiments, the supervisor module 210 may determine that an application has not failed in a predetermined time period. The supervisor module 210 may set the failed count to zero in response to determining that the application has not failed in the predetermined time period. In some embodiments, the supervisor module 210 may determine that the application has failed in a predetermined time period and may increment the failed count in response to determining that the application has failed in the predetermined time period. In some embodiments, the supervisor module 210 may relaunch the application after incrementing the failed count. In some embodiments, the predetermined time period may be adjusted by a user of the computing system 200. In some embodiments, a supervisor module 210 may receive a command from a user to reset the failed count. In some embodiments, the command may be received through a command line interface 230. The supervisor module 210 may reset the failed count using a value received from the user.

At block 310, the main program 215 may determine a failsafe mode level corresponding to the failed count. In some embodiments, the main program 215 may include several different levels, where each level has a different degree of enabled functionality. In some embodiments, each level may be associated with a range to compare to the failed count. For example, a first failsafe mode level may be associated with 5-10 failed attempts to launch an application, while a second failsafe model level may be associated with 11-15 failed attempts to launch an application. Continuing with this example, when 5-10 failed attempts are registered, a first portion of functionality is disabled; when 11-15 failed attempts are registered, a second, larger portion functionality is disabled. The main program 215 may determine whether the received failed count falls within a specific range associated with a level and may select the failsafe mode level accordingly. In some embodiments, the main program 215 may determine that the failed count exceeds a predetermined threshold from a plurality of predetermined thresholds and may select the failsafe mode level from a plurality of failsafe mode levels based on determining the failed count exceeds the predetermined threshold.

At block 315, the main program 215 may initialize the failsafe mode level in response to determining the failsafe mode level corresponds to the failed count. In some embodiments, the main program 215 may receive a command from a user (e.g., via a command line interface 230) to enable a disabled functionality in the failsafe mode level. The main program 215 may enable the disabled functionality in response to receiving the command from the user.

In some embodiments, the application (e.g., main program) being initiated may have two phases: initialization and normal runtime. Once initialization has completed (e.g., in a failsafe level), the main program 215 may send a command to the supervisor module 210 to decrement the failed count by 1. This way, if the user enters a command to enable some disabled functionality, and this causes a failure, the failed count sent to the main program 215 will be the same count that was originally sent before the user tried to enable a functionality. This seeks to ensure that, if, for example, while the user is troubleshooting (e.g., live debugging), that the failed count does not continue to increase, thus entering a different failsafe mode level. This can avoid the need to change the environment while the user is attempting to debug the original problem.

In some embodiments, the application may fail again, before the main program 215 has a chance to decrement the failed count. The supervisor module 210 may update the failed count and may send the updated failed count to the main program 215. In some embodiments, the main program 215 may determine, based on the updated failed count, that a different failsafe mode level should be initialized. The main program 215 may initialize the selected failsafe mode level.

The present disclosure may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

Aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. 

What is claimed is:
 1. A computer-implemented method for establishing a failsafe mode for an electronic device, comprising: receiving a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determining a failsafe mode level corresponding to the failed count; and initializing the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.
 2. The computer-implemented method of claim 1, further comprising: determining the application has not failed in a predetermined time period; and setting the failed count to zero in response to determining the application has not failed in the predetermined time period.
 3. The computer-implemented method of claim 1, further comprising: determining the application has failed in a predetermined time period; incrementing the failed count in response to determining the application has failed in the predetermined time period; and re-launching the application.
 4. The computer-implemented method of claim 1, wherein determining the failsafe mode level corresponding to the failed count further comprises: determining the failed count exceeds a predetermined threshold from a plurality of predetermined thresholds; and selecting the failsafe mode level from a plurality of failsafe mode levels based on determining the failed count exceeds the predetermined threshold.
 5. The computer-implemented method of claim 1, further comprising: receiving a command from a user to enable a disabled functionality in the failsafe mode level; and enabling the disabled functionality by editing a configuration setting of the application in response to receiving the command from the user.
 6. The computer-implemented method of claim 1, further comprising: receiving an updated failed count; determining a second failsafe mode level corresponds to the updated failed count, wherein the second failsafe mode level has more disabled functionality than the failsafe mode level; and initializing the second failsafe mode level in response to determining the second failsafe mode level corresponds to the updated failed count.
 7. The computer-implemented method of claim 1, further comprising: receiving a command from a user to reset the failed count; and resetting the failed count using a value received from the user.
 8. A computer program product comprising a non-transitory storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method for establishing a failsafe mode for an electronic device, comprising: receiving a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determining a failsafe mode level corresponding to the failed count; and initializing the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.
 9. The computer program product of claim 8, wherein the method further comprises: determining the application has not failed in a predetermined time period; and setting the failed count to zero in response to determining the application has not failed in the predetermined time period.
 10. The computer program product of claim 8, wherein the method further comprises: determining the application has failed in a predetermined time period; incrementing the failed count in response to determining the application has failed in the predetermined time period; and re-launching the application.
 11. The computer program product of claim 8, wherein determining the failsafe mode level corresponding to the failed count further comprises: determining the failed count exceeds a predetermined threshold from a plurality of predetermined thresholds; and selecting the failsafe mode level from a plurality of failsafe mode levels based on determining the failed count exceeds the predetermined threshold.
 12. The computer program product of claim 8, wherein the method further comprises: receiving a command from a user to enable a disabled functionality in the failsafe mode level; and enabling the disabled functionality by editing a configuration setting of the application in response to receiving the command from the user.
 13. The computer program product of claim 8, wherein the method further comprises: receiving an updated failed count; determining a second failsafe mode level corresponds to the updated failed count, wherein the second failsafe mode level has more disabled functionality than the failsafe mode level; and initializing the second failsafe mode level in response to a determination the second failsafe mode level corresponds to the updated failed count.
 14. The computer program product of claim 8, wherein the method further comprises: receiving a command from a user to reset the failed count; and resetting the failed count using a value received from the user.
 15. A system for establishing a failsafe mode for an electronic device, comprising: a processing unit in communication with one or more types of memory, the processing unit configured to: receive a failed count indicative of a number of failed attempts to launch an application from a supervisor module; determine a failsafe mode level corresponding to the failed count; and initialize the failsafe mode level in response to determining the failsafe mode level corresponding to the failed count.
 16. The system of claim 15, wherein the processing unit is further configured to: determine the application has not failed in a predetermined time period; and set the failed count to zero in response to determining the application has not failed in the predetermined time period.
 17. The system of claim 15, wherein the processing unit is further configured to: determine the application has failed in a predetermined time period; increment the failed count in response to determining the application has failed in the predetermined time period; and re-launch the application.
 18. The system of claim 15, wherein to determine the failsafe mode level corresponding to the failed count, the processing unit is further configured to: determine the failed count exceeds a predetermined threshold from a plurality of predetermined thresholds; and select the failsafe mode level from a plurality of failsafe mode levels based on a determination the failed count exceeds the predetermined threshold.
 19. The system of claim 15, wherein the processing unit is further configured to: receive a command from a user to enable a disabled functionality in the failsafe mode level; and enable the disabled functionality by editing a configuration setting of the application in response to receiving the command from the user.
 20. The system of claim 15, wherein the processing unit is further configured to: receive an updated failed count; determine a second failsafe mode level corresponds to the updated failed count, wherein the second failsafe mode level has more disabled functionality than the failsafe mode level; and initialize the second failsafe mode level in response to a determination the second failsafe mode level corresponds to the updated failed count. 